Leakage - Delay Tradeoff in Wide-Bit Nanoscale CMOS Adders

The scaling of nanometer technology has had a major impact on the power dissipation of CMOS circuits. As transistor size decreases it has become apparent that leakage power is becoming a dominant fighting force against future technology. In this paper the importance of static power consumption on the design of new and advanced CMOS technology is explored with the investigation of leakage power reduction techniques and their implementation on embedded CMOS adder circuits. Four different adder topologies of bit sizes 16, 32 and 64, were implemented using technology nodes 22nm, 32nm, and 45nm. To reduce the leakage power dissipation of these adders three different types of leakage reduction techniques were implemented and simulated using Hspice to determine the leakage and delay. The results were analyzed and the optimal leakage reduction technique(s) for each nanometer adder design was determined.